Influence of plasma etching on Em

Influence of plasma etching on Em:

Stress transfer (SM) and low-K TDDB. When the device is working, there is current passing through the metal interconnect. Due to the momentum exchange between electrons and metal lattice, metal ions will drift under the influence of electron wind, which results in holes or hillocks in some parts of the wire. When the cavity growth leads to the increase of conductor resistance to a certain critical value or the formation of circuit break, then the electromigration failure occurs. In bulk metals, the current density is low (<104 A/cm2), and the electromigration occurs only at high temperatures near the melting point of the material. Thin film material is not, such as aluminum alloy wire deposition, due to the small cross-sectional area and has good heat dissipation conditions, the current density can be as high as 107 A/cm2, so at A lower temperature will occur electric migration. The force of the electronic wind acting on the metal ion is

FEM eJ = rho Z * (7-15)

Where, ρ is the metal resistivity; Z* is the effective charge of metal. Table 7.3 lists Z* values of some metal materials. A negative Z* value indicates that metal ions move towards the positive electrode. A positive Z* value indicates that metal ions move towards the negative electrode. The smaller the value of Z*, the stronger the resistance to electromigration. In the table, the Z* values of Al and Cu are negative, and both Al and Cu ions move to the positive electrode, while the Z* value of Cu is only 1/6 of that of Al, indicating that the anti-electromigration ability of Cu is far greater than that of Al.

Electromigration is a mass conservation transport process. When metal ions gather, local mechanical stress on the metal and the surrounding dielectric layer will increase. This local stress increase will lead to metal ions backflow (Blech effect). For shorter wires, the Blech effect can be strong enough to counteract the drifting ions so that telephone migration is suppressed. Electromigration is mainly caused by momentum transfer and diffusion effect, and momentum transfer is proportional to the current density circulating in the metal, and diffusion effect is proportional to the temperature in the metal. At present, Black model is commonly used to describe electromigration failure, and the failure time model is

TF=A0(J-Jcrit)-nexp(Ea/kBT)            (7-16)

Where, A0 is the coefficient related to process and material, and the difference of A0 makes the failure time a distribution. EM generally adopts lognormal failure time distribution. J is the current density; Jcrit is the critical current density, and only when J is greater than Jcrit will electromigration occur. N is the current density index; Ea is activation energy; T is temperature; B sub B is the Boltzmann constant.

The migration path of EM depends on the metal wire structure and actual process. For general logical products, aluminum alloy interconnect is used above 0.13μm, copper interconnect is used below 0.13μm. The structure and manufacturing process of the two kinds of wires are different, and the mechanism is also different. Aluminum wire in aluminum alloy interconnection structure is formed by deposition and etching. It is a two-dimensional structure with large grain size. When the wire width is less than the average size of the grain, the wire is a bamboo-like structure. The copper wire and through hole in the copper interconnection structure are formed by Dual Damascene (DD) process and CMP. They are three-dimensional structure with small grain size. Moreover, due to the introduction of the copper diffusion shield layer, there will be a metal barrier layer TAN separated at the junction between the bottom of the through hole and the lower metal. Generally speaking, the surface of aluminum interconnect is covered with a layer of oxide film Al2O3, which has a strong bonding energy with the aluminum body, so the electromigration in aluminum mainly takes place along the grain boundary. When the line width becomes smaller and presents a bambus-like structure, the lattice migration becomes the main mechanism. However, the bond between the oxide CuO on the surface of Cu and the Cu body is relatively poor, and this interface provides a high fluidity channel for the migration of copper ions. In the current typical copper interconnection process, there is a dielectric barrier layer Sicon on the upper surface of copper to block Cu diffusion and act as an etching stop layer. Therefore, electrical migration in copper structure is mainly carried out along the interface between Cu and the dielectric barrier layer Sicon. The use of plasma to clean up the autooxidation layer of copper and silicify the copper surface prior to the deposition of the dielectric barrier layer can effectively improve the EM. Coating the copper surface with an alloy that can fix the copper ions and inhibit their diffusion is another way to greatly improve the EM, such as depositing a very thin layer of CO or COWP.

There are two kinds of electromigration test structures, namely, upline and downlink. Double Damascus copper interconnect technology zhongtong hole connected to the fluctuation of metal layer is a complex structure, the uplink electromigration structure, due to the small size of the upper metal, wide hole depth is larger, the upside of the structure of the hole is filled with a challenge, if the copper on the hole wall when filling metal barrier coverage discontinuity or uneven, will cause ascending EM failure; However, due to the large size of the upper metal, the failure of the lower electromigration structure is mainly due to the complex interface between the metal barrier layer at the bottom of the through hole and the lower metal copper. Zhao et al. studied the influence of the crack like void at the bottom of the through hole on the downlink EM, and found that appropriate post-etching cleaning process could effectively remove the copper oxide and etching residues at the bottom of the through hole, reduce the crack like void, and then significantly improve the downlink electromobility performance.

Generally, downlink migration failure occurs faster than uplink migration failure in copper interconnection. However, if there is a cavity defect in the through-hole of uplink structure, uplink migration failure will occur quickly and lead to early failure. As the size of IC features shuts down, copper filling in double large shuts processes is a great challenge. The dimensions and morphology of pits and through holes defined by etching are critical for good copper filling. Liu et al. systematically studied the relationship between the critical dimensions of the double damask structure and the early EM failure. In the figure, the etched double Damascus structure, MH is the depth of the groove, VH is the depth of the through hole, D1 is the size of the upper opening of the through hole at the inclined plane, and D2 is the size of the bottom of the through hole. According to these parameters, two key depth-width ratios can be further defined, namely, through hole depth-width ratio Via Ar = Vh/D2 and Chamfer Ar = Mh/D1. The cavity causing EM failure occurs in the through hole, which is called as the through hole failure mode. The cavity causing the EM failure occurs in the bevel area above the through hole, which is called the bevel failure mode. By reducing the thickness of dielectric material, reducing the depth of groove etching or increasing the key size of through-hole, the depth-width ratio can be reduced and the early failure of upward EM can be effectively reduced from the face. It should be pointed out that reducing the thickness of dielectric materials and metal conductors between layers will increase RC delay, and increasing the key size of the through hole will cause the dielectric TDDB problem related to the through hole, so it is necessary to find a balance between EM, electrical parameters and TDDB.

Under the condition of keeping the same size at the bottom of the through-hole, by adjusting the etching process to increase the size of the opening at the inclined surface of the through-hole and present a smooth morphology, the upping EM can be improved without other side effects. The smooth and large beveled opening is more favorable to cover the metal barrier layer in the through hole than the rectangular and small opening, and makes the current density distribution more uniform, which reduces the current density gradient at the beveled surface, so it has better upward EM performance.

Zhou et al. studied the relationship between the through-hole morphology and the early failure of upline EM. Under the DD etching process of the two etching machines, the early failure of uplink EM was observed, which reflected a few flying points in the distribution map. It was found through section that the early failure of these samples was caused by the uneven coverage of the metal barrier layer at the inclined surface inside the through-hole. The groove etching process in DD etching and the height of organic matter in the through-hole before groove etching determine the through-hole morphology, and the through-hole morphology must adapt to the uniformity of metal barrier layer deposition process, in order to achieve uniform metal barrier layer coverage on the inclined plane of the whole wafer. After the process is developed, the groove etching process is fixed, and only the steps to adjust the embolization height can be changed. By using uniform experimental design, a suitable process was found for a few experiments. Although the uniformity of the etching rate of the whole wafer decreased, it was combined with the barrier deposition process to eliminate the early failure of uplink EM.