The influence of plasma etching on PID

The influence of plasma etching on PID:

Plasmae Induced Damage (PID) refers to the performance deviation of MOSFET devices caused by various plasma processes in integrated circuit manufacturing. In the plasma environment, due to the discharge of a large number of ions and electrons, ions are accelerated and move towards the surface of the wafer due to the action of electrode potential or plasma self-bias, they have physical bombardment to the substrate and promote the chemical reaction on the surface. These ions and electronic currents are collected by the metal exposed to the plasma, which accumulates at the gate electrode of polycrystalline silicon or aluminum. At this time, the metal layer acts as an "antenna". The gate oxide layer can be regarded as a capacitor. Under the action of FN current, the gate oxide layer and interface will produce defects, the resulting damage will lead to the reduction of IC yield, and will accelerate the degradation of hot carrier and TDDB effect, causing long-term reliability problems of devices. The degradation of gate oxide layer caused by charging effect is a serious problem in IC fabrication.

There are several main mechanisms causing PID:

(1) Plasma density. Higher plasma density means higher current Under the charge-induced damage model, higher plasma density is more likely to cause PID problems. Krishnan et al. found that when the height of ICP metal etching reaction chamber was reduced from 8cm to 5cm, the electric field intensity on the wafer surface was significantly enhanced. The increase of plasma density leads to charge charging, which causes serious device damage.

(2) Local inhomogeneity of plasma. In a uniform plasma, ion and electron currents balance in one RF cycle, so the gate oxide potential is very small, but in an inhomogeneous plasma, the potential imbalance in a local range will generate current paths on the surface of the wafer, which will cause the gate oxide damage.

(3) Eletron Shading Effect. Electrons in plasma have worse directionality than ions, that is, the incidence Angle distribution of electrons is larger than that of ions, which is easier to be blocked by photoresistance. The positive ions gather in the front end of the etching to form the positive potential of the device.

(4) Reverse Electron Shading Effect. ESE occurs in areas with dense patterns, such as patterns with spacing less than 0.5μm. On the contrary, in the open region of the pattern, such as the pattern spacing greater than 2μm, due to the isotropy of the electrons. Some of the electrons are collected by the side wall of the metal to be etched, while the ions are not, resulting in a negative charge accumulating on the side wall of the metal forming a negative potential against the device.

(5) VUV Radiation. A large number of VUV photons are produced during plasma discharge, which causes photocurrent in the gate oxide layer and damages the device. Si3N4, which has a narrower band gap than Si3N4 at the top of the gate, can effectively absorb and block high-energy VUV, so as to protect the gate oxide layer from damage by VUV radiation.

Studies have shown that when the Ratio of Antenna area to device size is larger, the damage of the device is more serious. Antenna ratios of different sizes can be designed to compare the damage degree of the device caused by different plasma processes. Generally, gate leakage current is used to characterize PID. Taking NMOS as an example, the greater the leakage current, the more serious the PID caused by positive charge.

In circuit design, the influence of PID can be effectively inhibited by avoiding high antenna ratio, adopting metal jump layer or using protective diode to introduce charge into the substrate, and the antenna ratio that can be tolerated by the device can be improved by process optimization. Zhou et al. independently tested and analyzed the PID introduced in each layer metal manufacturing process to study the influence of various back-stage etching processes on PID. The dielectric etching of the metal layer charges the metal antenna of the contact hole, and the PID problem is generated when the antenna ratio of the contact hole is very small (e.g. 20), while the PID problem is generated when the antenna ratio of the high level metal is several thousand. The longer the over-etching time of metal layer is, the worse the PID will be. The higher the ratio of high frequency power to low frequency power is, the worse the PID will be. When the power supply is replaced with a higher frequency power supply, the more serious the PID problem will be, because the higher the power supply frequency is, the higher the plasma density is, the more serious the corresponding charge aggregation phenomenon is, so the worse the PID will be. However, the high frequency power is very important for the control of polymer by-products in etching, so the choice of frequency should be carefully weighed. For the passivation layer etching, the influence of the etching time on PID is not significant, probably because the receiving antenna is copper, while the metal layer etching is tungsten, the sensitivity is different, and the distance from the front part of the device is too far. In the etching of the second passivation layer, it is also insensitive to over-etching time, but the use of magnetic field will bring serious PID problems. Compared with the process without magnetic field, the use of magnetic field can improve the etching uniformity, but the excessive plasma density brought by it has a great impact on PID. Is different from the above process due to the positive charge accumulation and the PMOS PID, the aluminum liner etching would cause the problem of PID of NMOS, it can use the RESE model and charge collection effect of ultra-thin metal layer to explain, aluminum liner graphic spacing generally larger, and it is the metal etching, in line with the RESE model, on the other hand, when the metal etching draws to a close, ultra-thin AI film easy to collect negative charge, gathered the negative charge of the NMOS gate oxide generated from the basement to grid FN current, damage the gate oxide.

The HKMG technology adopted by the advanced technology node brings greater challenges to PID. In the plasma pseudo grid removal process, must clear in the corner of the polysilicon, need to put a long time based on NF3 / H2 gas etching, but as a result of direct contact with the plasma High - k gate dielectric layer on the work function of the metal, the hydrogen ions in plasma greatly increases the damage of gate dielectric layer, Ji and others speculate that the sync pulse plasma to ensure corner the absence of polycrystalline silicon residue, by reducing the electron temperature to relieve the damage of the gate dielectric layer. Because of these challenges, the industry has developed a process for deposition of high-K gate dielectric layer after pseudo gate removal. In pseudo gate removal, a part of the dielectric layer is etched by plasma and then the remaining part is removed by chemical solvent, which effectively avoids the damage of the dielectric layer caused by plasma etching.