Etching process in plasma Cleaning Machine 3DNAND

Etching process in plasma Cleaning Machine 3DNAND:

Compared with planar NAND flash process, 3DNAND has great changes in device structure, and the corresponding plasma surface processor plasma cleaning machine etching process is also very different from the past. The main new features of the process are around the 3D structure preparation, including the step etching; Channel through hole etching; Notch etching; Contact hole etching.

1. Plasma surface treatment machine plasma cleaning machine step etching

The purpose of step etching is to connect each control grid layer separately for subsequent processes. As the control grid layer is in a stacked state, it needs to be extended to different degrees in the horizontal direction, while the contact hole structure prepared by the subsequent process connects different control grid layers and connects the interconnection circuit of the back segment for separate control.

Plasma surface treatment Plasma cleaning machine step etching target material for SiO2 and Si3N4 stack structure, each step etching stop on the lower SiO2 surface. The step extension structure is formed by the reduction of the mask layer (generally photoresist), and the reduced size is transmitted to the target material supplier through the SiO2/Si3N4 etching process. The etching process is cycle etching.

This process is usually accomplished using plasma cleaner inductively coupled plasma etching (ICP) models. The main control requirements are the consistency of each cycle size reduction during the photoresist reduction process, the edge roughness control, the degree of average size reduction on the entire wafer, and the selectivity of the SiO2/Si3N4 etching process for photoresist reduction. The accuracy of step width determines whether subsequent contact holes are properly connected to the specified control grid layer.

Since the width of each step (i.e., the extension size of each control gate layer) is required to be hundreds of nanometers so that the subsequent contact hole can fall safely and accurately on the required control gate layer, each reduction process of photoresist mask layer in the cycling process requires a unilateral reduction of hundreds of nanometers. Generally, the etching gas is dominated by O2 to achieve a sufficiently high reduction rate.

In the cyclic etching process, SiO2 and Si3N4 are etched and stopped on the lower SiO2 surface in a single time. Due to the need of selection ratio, they are generally decomposed into the steps of SiO2 etching (with a relatively low selection ratio) and Si3N4 etching, which requires a higher selection ratio for SiO2 to stop on the lower SiO2 surface. Usually, SiO2 is etched with etching gases with a relatively low carbon-fluorine ratio such as CF4/CHF3, while Si3N4 is etched with etching gases with a relatively high carbon-fluorine ratio such as CH2F2. The latter has a relatively low bias to provide an adequate selection ratio for SiO2.

The total thickness of a pair of SiO2/Si3N4 layers in the industry mainstream is not more than 15nm, far less than the width of steps of hundreds of nanometers. The SiO2/Si3N4 etching requires relatively loose side wall Angle and does not need to be close to vertical. This is conducive to etching process adjustment to meet limited selection ratio requirements for SiO2 and photoresist.

2. Channel through hole etching for plasma cleaning machine of plasma surface processor

The preparation of channel through hole structure consists of two processes: mask etching and channel through hole etching.

(1) Channel through hole hard mask etching

With the increase of capacity, the number of control grid layers has been gradually increased from 24 to 48, and more layers of devices are still under development. However, the channel through hole etching needs to etch through all SiO2/Si3O4 film pairs at one time. Compared with the contact hole depth of less than 200nm for the standard logic process (45nm process node), the 3D NAND middle channel hole depth is more than 400nm (early 24-layer 3D NAND structure). If 128 layers of control gate layer is to be realized, the channel through hole is more than L m. So channel through hole etching generally adopts hard mask etching process.

This process is usually accomplished using plasma Surface treatment plasma Cleaner induced coupled plasma etching (ICP) models. According to the 3D NAND structure difference (mainly the difference in the number of gate layers), the hard mask material is mainly amorphous carbon. The etching gas is dominated by O2 or N2/H2 combination gas.

The control requirements of mask etching mainly include:

Graphic transfer accuracy. Avoid graphics deformation in etching process resulting in inaccurate graphics of channel through hole. Hardmask side walls need to be coherent and as vertical as possible. In the subsequent etching of 10 pairs of SiO2/Si3N4 thin film pairs, hard mask was used as the barrier layer. Defects in the hard mask side wall would be transferred to SiO2/Si3N4 thin film pairs in the subsequent etching process.
The key size is one degree.

(2) Channel through hole etching of plasma surface treatment machine

Dozens of pairs of SiO2/Si3N4 films for channel-through hole etching have great challenges due to their ultra-high aspect ratio. In the standard logic process as a reference, the depth-width ratio of contact holes is generally 4~7, while the depth-width ratio of CONTACT holes in 3D NAND is generally above 10, which increases with the increase of the number of control grid layers. Accordingly, plasma surface processor etcher manufacturers developed HAR Etch models to meet the 3D NAND process requirements.

This process is usually accomplished using a plasma Surface treatment plasma cleaner with capacitive coupled plasma etching (CCP) machine.

There are three main challenges in the aspect ratio etching process, including the deformation of the side wall at the bottom of the through-hole due to the uneven distribution of plasma at the bottom; The selective ratio of layer height of hard mask leads to uneven distribution of etched protective layer and deformation of upper side wall of through hole. And in the process of etching, as the depth of the through-hole gets deeper and deeper, it is difficult for the plasma to reach the bottom of the through-hole, which causes the etching to stop.

In etching process using multiple steps the cycle of repeated "etching a exhaust" technology makes etching layer distribution more uniform, while increasing the bias power to logical process usually use range of 5 ~ 10 times, in order to improve the plasma's ability to reach the bottom of the hole, at the same time extend the process window using a lower pressure and higher gas flow rate to rule out the bottom of the hole etching products, so as to solve the above problems.

The etching gas was selected as the SiO2 etching process in the classic CCP cavity, and the mixed gas with different carbon and fluorine ratios (such as CH2F2, C4F6 and C4F8) was used to realize the side wall Angle, selection ratio and other considerations.

The control requirements of channel through hole etching mainly include:

Hard mask layer selectivity;
Continuity of side wall through hole;
Angle of side wall through hole.

3. Plasma surface processor, plasma cleaning machine, notch etching

Channel through hole etching is the same as the target material of notch etching, the difference lies in that the former is a hole while the latter is a groove. In the process of implementation, the etching-protection balance is different because of the difference of graphics. At the same time, it also leads to the difference of working environment of etching machine cavity. Because channel through hole etching and notch etching require very high process precision, in order to avoid the unstable working environment of etching cavity caused by the two processes, the mainstream manufacturers generally use separate etching machine to complete the corresponding process respectively.

The control requirements for notch etching are similar to those for channel through hole etching.

4. Plasma surface processor, plasma cleaning machine, contact hole etching

The contact hole etching of 3D NAND also belongs to the high aspect ratio etching process. Different from the channelthrough hole process, the contact hole etching material is a single SiO2, but the depth of each contact hole is different because it stops at different control grid layers. In the process of contact hole etching at different depths, the amount of overetch varies greatly. In addition to the three main challenges arising from the medium to high aspect ratio of the channel through hole, contact hole etching needs to provide a higher selection ratio for the etch stop layer.

This process is usually accomplished using a plasma Surface treatment plasma cleaner with capacitive coupled plasma etching (CCP) machine.

Similar to the process requirements of channel-through hole etching, contact hole etching also requires a stronger bias power than logical etching, usually requiring an increase of three times or higher. At the same time, a lower frequency bias power is used to provide a longer ion free path to improve the ability of the etched plasma to reach the bottom of the contact hole, thus avoiding the deformation of the side wall at the bottom of the contact hole and reducing the possibility of stopping the etching.

At the same time, advanced models on the market offer a wide variety of pulse plasma generation methods, including individual high frequency, low frequency and DC pulses, or high and low frequency synchronous pulses.