Development of offset side walls

• Categories:Industry News
• Author:plasma cleaning machine-surface treatment equipment-CRF plasma machine-Sing Fung Intelligent Manufacturing
• Origin:
• Time of issue:2020-12-09
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(Summary description)The process with gate size below 1.0 PM is called sub-micron process. And below 0.25 PM, we call it deep submicron process. In the submicron and deep submicron age, with the decrease of gate length/Channel length, the main technical problem we faced was not only Punch Through, but also the hot carrier effect caused by Channel Electric Field. The main reason was that the width of the depletion zone extended to enter the channel, resulting in the narrowing of the effective channel length, so the equivalent electric field added on the channel increased (Vd/Leff), which gave rise to the occurrence of Electron hole Pair in the channel, and thus formed Hot carrier Injection (HCE or HCI).   The effective length of channel can only be improved by reducing the width of depletion zone. On the one hand, the width extension of depletion zone can be inhibited by increasing the concentration of channel area, NAPTimplant or Pocket implant used in advanced technology. On the other hand, the concentration of PN junction in the source leakage area is reduced, which can also reduce the width of the depletion area. The former can inhibit penetration, but it is impossible to increase the concentration all the time, after all, it will affect the opening voltage of the channel. For the latter, a low-doped LDD is adopted as the transition zone of the Junction of N+_Source/Drain, and the PN Junction of N+/PW is transferred to NLDD-/P Well, so the width of the depletion zone on the side of PW is naturally narrowed.   From the perspective of device structure, the offset side wall width size adjacent to the gate can control the position of LDD relative to the gate, or the distance of L.D doped to the bottom of the gate to achieve the purpose of controlling the gate - drain overlapped capacitance (CGDO). The rear main side wall (MainSpacer) will be injected into the following high-concentration source leakage area, so that the LDD area can be retained and a self-aligned source leakage area can be formed at the same time.   To form the side wall, a thin film is first deposited on the gate. Assuming that the thickness of the film deposition is A and the grid height is B, the height of the side wall beside the grid is A + B. Our side wall etching is backetching and anisotropic etching, which can be equivalently understood as only downward etching with little or no side etching, so if the etching amount is thickness A, the gate side wall will be left with only side wall residual, which is the side wall we want. For the main side wall, its width is the length of LDD, and its width is determined by the thickness of the deposited film, of course, the etching itself can also affect the width of the side wall.   In the submicron age, TEOS silicon oxide (TEOS silicon oxide) is deposited directly on the gate, and then the etching stops on the source leakage silicon to form the side wall. The problem with this approach is that it causes damage to the silicon. So when the device is reduced to a certain size, leakage becomes uncontrollable. Then came the 0.25 m era when the silicon oxide side wall of TEOS could not meet the requirements of the process, so the silicon nitride side wall was developed later. Because the etching of the si3N4 side wall can stop ON the silicon Oxide layer below, it has no effect ON the silicon. Such side wall is also called the silicon nitride side wall or the Oxide SiN (ON) side wall.   At an age of 0.18 m, the stress on the si3N4 side wall will decrease saturation current and increase leakage. In order to reduce the stress, the deposition temperature needs to be raised to 700℃, and the heat cost of mass production will increase, which will also increase the leakage. Therefore, ONO side wall was selected in the 0.18 m era. The bottom is also the silicon oxide formed by Rapid Thermal Oxidation (RTO), and then a thin layer of silicon nitride is deposited in the middle, followed by a layer of TEOS silicon oxide. Firstly, the silicon oxide of TEOS is etched, and the silicon nitride is stopped, and then the silicon nitride is etched and stopped on the silicon oxide of RTO. In this way, the stress and thermal cost requirements are satisfied, and there is no damage to the substrate. When it comes to the age below 65nm, the stress is no longer an important influence due to the reduction of side wall thickness. ON side wall is once again widely used in advanced semiconductor technology due to its advantages of simple process and stable control.