Polysilicon gate etching in fin-type FET of plasma Surface Treatment instrument

• Categories:Technical Support
• Author:plasma cleaning machine-surface treatment equipment-CRF plasma machine-Sing Fung Intelligent Manufacturing
• Origin:
• Time of issue:2020-12-08
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(Summary description)FinFET still uses the dual-graphics method in the planar transistor at 28nm to define gate lines and line ends. Different from the planar transistor, FinFET is a THREE-DIMENSIONAL transistor, and the polysilicon gate is across the fin. This difference leads to the difference in the etching process of the plasma surface treatment instrument. The profile morphology after polycrystalline gate etching has great influence on the subsequent process. The morphology at the top and bottom of polysilicon will affect the growth performance of stress sige. An ideal profile etched by polysilicon plasma surface treatment instrument will have the residue of hard mask on the polysilicon. The profile of polysilicon is a very vertical morphology, which is the same as the key size of hard mask.   Lateral etching occurs in polysilicon etching. When the plasma surface treatment etching process has different etching selection ratio for hard mask and polysilicon, the key size of the top of polysilicon will be different from the hard mask. For example, when a polysilicon key size is greater than the critical size of hard mask, the bias side walls in the subsequent p-type Silicon germanium grooves (PMOS Silicon Recess, PSR) plasma surface treatment instrument etching will receive more consumption, once the bias side wall thickness is not enough to protect the top of the polycrystalline Silicon, Silicon germanium in subsequent epitaxial growth, there is a big chance to grow on top of the poly Silicon germanium epitaxial forming defects, cause device failure; When the key size of polysilicon is smaller than that of hardmask, the occurrence of such defects will be much less, which is beneficial to improve the yield. Similarly, when the polysilicon has relatively serious bottom length after etching, the offset side wall at the bottom will also suffer more consumption in PSR etching, which leads to silicon and germanium defects growing at the bottom of polysilicon in subsequent silicon and germanium epitaxy. When the effective height of the hard mask is not enough, silicon and germanium defects will also grow in the top polysilicon, so it is particularly important to control the etched profile morphology in the FinFET polysilicon.   As a THREE-DIMENSIONAL transistor, the channel factor must be considered in the etching of polysilicon. The fin itself is made of bulk silicon. When the plasma surface treatment instrument etches polysilicon, the loss of the fin itself still needs to be considered in spite of the protection of silicon oxide. In the etching process, the etching process is usually switched to the traditional high selection ratio HBr/O2 step when it is 200~300 from the top of the fin, and a lower bias power is required. Also because of the existence of three-dimensional fins of the top above the top part and the following partial etching of polysilicon gate environment is different, so in the process of the plasma surface treatment instrument etching to form ideal polysilicon gate section morphology, usually have high selectivity, soft landing steps into a few steps to achieve the goal of optimization of polysilicon section morphology. Since the epitaxy of the source drain is formed directly on the fin, this means that the fin loss in FinFET polysilicon etching becomes less important than that in planar substrate silicon etching. To ensure the subsequent epitaxial growth, the polysilicon in the corner where the fin intersects the gate needs to be cleaned, so from the perspective of device integration, fin loss is inevitable.