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Research on WAT method used in integrated circuit manufacturing in plasma CMOS process

  • Categories:Company Dynamics
  • Author:Plasma cleaning machine-CRF plasma plasma equipment-plasma surface treatment machine manufacturer-chengfeng intelligent manufacturing
  • Origin:
  • Time of issue:2022-01-22
  • Views:

(Summary description)Research on WAT method used in integrated circuit manufacturing in plasma CMOS process: WAT (Wafer Accept Test) is the silicon wafer acceptance test, which is to conduct electrical tests on various test structures on the silicon wafer after the semiconductor silicon wafer has completed all the manufacturing processes. It is a means of reflecting product quality. A quality inspection before products are put into storage. With the development of semiconductor technology, plasma technology has been widely used in the manufacture of integrated circuits. Ion implantation, dry etching, dry debonding, UV radiation, film deposition, etc. may introduce plasma damage. The WAT structure cannot be monitored and can lead to early failure of the device. Plasma processes are widely used in integrated circuit manufacturing, such as plasma etching, plasma enhanced chemical vapor deposition, ion implantation, and the like. It has the advantages of good directionality, fast reaction, low temperature and good uniformity. However, it also brings charge damage. As the thickness of the gate oxide layer continues to decrease, this damage will increasingly affect the reliability of the MOS device, because it can affect the fixed charge density and interface state density in the oxide layer. , flat-band voltage, leakage current and other parameters. Large-area ion-collecting regions (polycrystalline or metallic) with antenna device structures are typically located on thick field oxides, so only the tunneling current effects on thin gate oxides need to be considered. The large-area collection area is called the antenna, and the tunnel current amplification factor of the device with antenna is equal to the ratio of the area of ​​the collection area on the thick field oxide to the area of ​​the gate oxide area, which is called the antenna ratio. If the gate oxide area is small and the gate area is large, the ions collected by the large-area gate will flow to the small-area gate oxide area. In order to maintain charge balance, the tunnel current injected into the gate by the substrate also needs to follow Increase, the multiple of increase is the ratio of gate to gate oxide area, amplifying the damage effect, this phenomenon is called "antenna effect". In the case of gate implantation, the sum of the tunneling and ionic currents equals the total electron current in the plasma. Because the current is very large, even without the amplification effect of the antenna, as long as the field strength in the gate oxide can generate tunneling current, it will cause plasma damage. In normal circuit design, the gate terminal generally needs to be opened through polysilicon or metal interconnects to be the functional input terminal, which is equivalent to introducing an antenna structure on the weak gate oxide layer, so in normal tape-out and WAT monitoring The electrical test and data analysis of the single-tube device carried out at the time cannot reflect the actual plasma damage in the circuit. The oxide layer continues to be thinned to below 3nm, and the problem of charging damage is basically no longer considered, because for the oxide layer with a thickness of 3nm, the charge accumulation is directly tunneling through the barrier of the peroxide layer, and no charge defects will be formed in the oxide layer.

Research on WAT method used in integrated circuit manufacturing in plasma CMOS process

(Summary description)Research on WAT method used in integrated circuit manufacturing in plasma CMOS process:
WAT (Wafer Accept Test) is the silicon wafer acceptance test, which is to conduct electrical tests on various test structures on the silicon wafer after the semiconductor silicon wafer has completed all the manufacturing processes. It is a means of reflecting product quality. A quality inspection before products are put into storage.
With the development of semiconductor technology, plasma technology has been widely used in the manufacture of integrated circuits. Ion implantation, dry etching, dry debonding, UV radiation, film deposition, etc. may introduce plasma damage. The WAT structure cannot be monitored and can lead to early failure of the device. Plasma processes are widely used in integrated circuit manufacturing, such as plasma etching, plasma enhanced chemical vapor deposition, ion implantation, and the like. It has the advantages of good directionality, fast reaction, low temperature and good uniformity.
However, it also brings charge damage. As the thickness of the gate oxide layer continues to decrease, this damage will increasingly affect the reliability of the MOS device, because it can affect the fixed charge density and interface state density in the oxide layer. , flat-band voltage, leakage current and other parameters. Large-area ion-collecting regions (polycrystalline or metallic) with antenna device structures are typically located on thick field oxides, so only the tunneling current effects on thin gate oxides need to be considered. The large-area collection area is called the antenna, and the tunnel current amplification factor of the device with antenna is equal to the ratio of the area of ​​the collection area on the thick field oxide to the area of ​​the gate oxide area, which is called the antenna ratio.
If the gate oxide area is small and the gate area is large, the ions collected by the large-area gate will flow to the small-area gate oxide area. In order to maintain charge balance, the tunnel current injected into the gate by the substrate also needs to follow Increase, the multiple of increase is the ratio of gate to gate oxide area, amplifying the damage effect, this phenomenon is called "antenna effect". In the case of gate implantation, the sum of the tunneling and ionic currents equals the total electron current in the plasma. Because the current is very large, even without the amplification effect of the antenna, as long as the field strength in the gate oxide can generate tunneling current, it will cause plasma damage.
In normal circuit design, the gate terminal generally needs to be opened through polysilicon or metal interconnects to be the functional input terminal, which is equivalent to introducing an antenna structure on the weak gate oxide layer, so in normal tape-out and WAT monitoring The electrical test and data analysis of the single-tube device carried out at the time cannot reflect the actual plasma damage in the circuit. The oxide layer continues to be thinned to below 3nm, and the problem of charging damage is basically no longer considered, because for the oxide layer with a thickness of 3nm, the charge accumulation is directly tunneling through the barrier of the peroxide layer, and no charge defects will be formed in the oxide layer.

  • Categories:Company Dynamics
  • Author:Plasma cleaning machine-CRF plasma plasma equipment-plasma surface treatment machine manufacturer-chengfeng intelligent manufacturing
  • Origin:
  • Time of issue:2022-01-22 21:46
  • Views:
Information

Research on WAT method used in integrated circuit manufacturing in plasma CMOS process:
WAT (Wafer Accept Test) is the silicon wafer acceptance test, which is to conduct electrical tests on various test structures on the silicon wafer after the semiconductor silicon wafer has completed all the manufacturing processes. It is a means of reflecting product quality. A quality inspection before products are put into storage.

With the development of semiconductor technology, plasma technology has been widely used in the manufacture of integrated circuits. Ion implantation, dry etching, dry debonding, UV radiation, film deposition, etc. may introduce plasma damage. The WAT structure cannot be monitored and can lead to early failure of the device. Plasma processes are widely used in integrated circuit manufacturing, such as plasma etching, plasma enhanced chemical vapor deposition, ion implantation, and the like. It has the advantages of good directionality, fast reaction, low temperature and good uniformity.
However, it also brings charge damage. As the thickness of the gate oxide layer continues to decrease, this damage will increasingly affect the reliability of the MOS device, because it can affect the fixed charge density and interface state density in the oxide layer. , flat-band voltage, leakage current and other parameters. Large-area ion-collecting regions (polycrystalline or metallic) with antenna device structures are typically located on thick field oxides, so only the tunneling current effects on thin gate oxides need to be considered. The large-area collection area is called the antenna, and the tunnel current amplification factor of the device with antenna is equal to the ratio of the area of ​​the collection area on the thick field oxide to the area of ​​the gate oxide area, which is called the antenna ratio.
If the gate oxide area is small and the gate area is large, the ions collected by the large-area gate will flow to the small-area gate oxide area. In order to maintain charge balance, the tunnel current injected into the gate by the substrate also needs to follow Increase, the multiple of increase is the ratio of gate to gate oxide area, amplifying the damage effect, this phenomenon is called "antenna effect". In the case of gate implantation, the sum of the tunneling and ionic currents equals the total electron current in the plasma. Because the current is very large, even without the amplification effect of the antenna, as long as the field strength in the gate oxide can generate tunneling current, it will cause plasma damage.
In normal circuit design, the gate terminal generally needs to be opened through polysilicon or metal interconnects to be the functional input terminal, which is equivalent to introducing an antenna structure on the weak gate oxide layer, so in normal tape-out and WAT monitoring The electrical test and data analysis of the single-tube device carried out at the time cannot reflect the actual plasma damage in the circuit. The oxide layer continues to be thinned to below 3nm, and the problem of charging damage is basically no longer considered, because for the oxide layer with a thickness of 3nm, the charge accumulation is directly tunneling through the barrier of the peroxide layer, and no charge defects will be formed in the oxide layer.

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