Effect of plasma etching on low-K TDDB

Effect of plasma etching on low-K TDDB:
At advanced technology junctions, the dielectric interval of the metal layer in the back section is reduced to less than 100nm, and the introduction of low-K materials to reduce RC delay greatly reduces the mechanical properties of the dielectric and increases the number of defects. These adverse factors lead to more and more serious dielectric breakdown problems between metal interconnects. The TDDB of low-K is similar to the TDDB of gate oxide we discussed earlier, but it is also very different. One is that the gate oxide layer is longitudinal breakdown, and the graphical process has limited influence on it, but the low-k at the back section is generally transverse breakdown, and the Cd, morphology and LWR determined by the graphical process have a decisive influence on it. Secondly, the Cu chemical mechanical grinding process introduced in the copper interconnection will lead to metal ion residue and water vapor invasion, which are not found in the gate oxide layer. In addition, plasma damage to low-K during etching and metal barrier sputtering deposition is also unique to low-K TDDB. Although the dielectric spacing of the back segment is much thicker than the gate oxide layer thickness of the same node, for example, the gate oxide layer of the advanced technology node is only about 2nm, the dielectric spacing of the back segment can reach about 35nm, but due to the complex material properties and process, the low-K breakdown is no less challenging than the gate oxide layer breakdown.

Low k material SiCOH leakage current under the condition of high temperature and high pressure stress change with time, the initial phase can be observed clearly the current decline, general is limited due to charge in the dielectric, with stress, keep up trap charge induced leakage current increase slowly, this phase will last a long time, until the current rapid increase, is the breakdown. The typical Cu/ Low-K breakdown mode is generally along the interface between Low-K and the overburden layer, and there is obvious Cu ion diffusion.
Breakdown may be the breakdown of the internal bonds in the dielectric, or the diffusion of metal into the insulation. The failure time model is needed to extrapolate the test results from the high voltage to the low voltage, i.e. the operating voltage. There are two widely known models for dielectric breakdown of metal layers. One is the thermochemical breakdown model, in which the Si-O bond breaks at high pressure, which is intrinsic failure; the other is the charge injection model, in which the copper ion diffuses into the human dielectric and leads to breakdown, which is unintrinsic breakdown. For the back-segment Cu/ low-K structure TDDB, the influence of Cu electrode is very significant due to the high dispersion of Cu and the instability of copper oxide. At present, most people in the industry accept the latter model, also known as the interface breakdown model driven by current and catalyzed by copper ions. In this model, the accelerated electrons from the cathode are injected into the anode by either Schottky emission or Poole-Frenkel emission. The Schottky emission corresponds to the low electric field condition (<1.4 mV /cm), which is the thermal excitation of electrons across the barrier at the metal-dielectric interface. And Poole - Frenkel emission corresponds to the high electric field (> 1.4 MV/cm), for the dielectric in trap electrons into the dielectric in electric field enhanced thermal excitation conduction band, the high energy electron after reaching anode, will part with CuO occurs on the surface of the anode electrochemical reaction produces copper ions, and then Cu ion diffusion or under the action of drift in the dielectric in electric field, a kind of Cu ion motion path for low - k and the top layer of interface. If there is no CuO on the surface of the copper electrode, but only Cu atoms, basically no copper will be observed to enter the dielectric, so the choice of grinding fluid during CMP, copper surface cleaning after CMP, CuO reduction in H2 environment, isolation of water vapor to avoid water oxidation of Cu are very important for low-K TDDB.
According to the Se and PF conduction current formulas and the assumption of the charge injection model that the damage degree of the dielectric is proportional to the amount of charge injected into the dielectric, the failure time when the dielectric damage reaches the critical point can be expressed as
TF = Aexp (-ϒE) exp (Ea/kBT) (7-18)
Among them, the ϒ for electric acceleration factor. Equation (7-18) is also known as the model root E of TDDB. The failure time of TDDB under low electric field can reach several years. More experimental results show that the failure time of Cu/ low-K structure under low electric field is closer to the failure time derived from the root E model, and the correctness of the root E model is confirmed through experiments.
By increasing the porosity in the low-K material, the K value can be effectively reduced, but the defects in the material will increase. When the dielectric interval is reduced to less than 30nm, the failure time of porous low-K materials at high voltages decreases sharply, and the failure time of porous low-K materials may not reach the life of consumer electronics even using the extramelized model. Oates et al. suggested that the two-stage defect nucleation and defect growth model should be used instead of the existing root E model which only considered defect nucleation to prolong the failure time of the extrapolation. Because defect growth is very rapid at high voltages, the measured failure time only represents the defect nucleation process, but at low voltages the defect growth is much slower and this time is not reflected in the model. The process of defect nucleation and growth can be characterized by the two-stage stress measurement technique. According to this method, the failure time of low-K TDDB can be extended several orders of magnitude. This method is still under discussion and needs more experimental data from the industry to verify.
The influence of plasma etching on low-K TDDB is mainly reflected in two aspects, one is the low-K damage caused by plasma etching, the other is the size and uniformity of the etching defined figure.
After SiCOH deposition of low-K material is completed, the molecular network structure of the material is stable and arranged regularly, but the etching process interrupts this structure. A large number of incomplete structures, namely defects, are formed on the side wall of the groove. At the same time, oxygen ions in the plasma can drill into the porous Low-K, bind to the C in the methyl group at the end of the molecular structure, and take it away, resulting in the depletion of surface carbon and further destroying the structure of Low-K. The plasma also emits a vacuum ultraviolet (VUV) light. Low-K absorbs these high-energy photons and causes chemical bonds to break, possibly forming low-energy conductive channels on the surface. These defects caused by plasma will become charge traps in TDDB test, which will trap charge under the action of stress and cause the potential barrier on the dielectric surface to decrease, thus accelerating the dielectric breakdown. Nichols et al. showed that the TDDB failure time of low-K materials treated by ECR plasma or irradiated by VUV was significantly shortened under various electric field intensifies.
Hydrofluoric acid can hardly etch SiCOH in low-K materials, but it can easily remove SiO2 produced after carbon depletion. In engineering, the SiCOH etched by plasma is generally treated with low concentration chlorofluoric acid (DHF), and the damage degree of SiCOH caused by plasma is characterized by observing the thickness of the carbon depletion layer. The P4 (Post Plasma Protection) method proposed by IBM can effectively reduce the damage of porous low-K materials during Plasma etching. Under different electric field intensification, the failure time of low-K materials after initial deposition and low-KTDDB after Plasma treatment or VUV irradiation. Solid line is VE model, (b) the comparison of carbon depletion layers with and without P4 Protection
The carbon depletion layer of low-K protected by P4 method is greatly reduced after etching, and the higher the porosity is, the more obvious the effect is. The specific method is as follows: after the porous Low K deposition is completed, the polymer is spin-coated on it, and then the polymer is heated to penetrate into the hole through capillary action. Then, the conventional graphic and metallization processes are performed, and the organic polymer in the hole is decomposed and released by heating to re-form the porous low-K dielectric. On the other hand, Imec found that there was almost no carbon depletion layer produced in the ultra-low temperature etching when the temperature was as low as -70℃, and the reaction by-products containing C, H, and O on the side wall liquefied and penetrated into the pores of the low-K film at ultra-low temperature, preventing plasma damage.
TDDB can be effectively improved by increasing the spacing between metal conductors and improving the uniformity of the spacing. The carbon depletion layer needs to be removed as far as possible due to its high K value, so reducing the thickness of the carbon depletion layer caused by plasma damage can effectively increase the width of the dielectric. Under a certain pitch, lead spacing increases means that lead and will bring conductor resistance larger, higher capacitance, and fill in the hole more difficult and so on, so in a conductor technology node spacing adjustable space is small, while improving mainly concentrated in uniformity, including local and whole uniformity of wafer, it is similar to the grid size uniformity discussed earlier. The local uniformity is characterized by Ler. The electric field intensity in the Cu protrusion area is much higher than that in other areas, and dielectric breakdown is more likely to occur. Through graphical optimization, such as the use of metal hard masks in groove etching, LER can be greatly improved. As the size of graphics decreases, the influence of LER becomes more and more significant, and how to improve LER through detailed graphics is an eternal topic. Since the groove after etching is always inclined to a certain Angle, such as 85°, the width of the dielectric upper surface is not only dependent on the size of the etching definition, but also depends on the depth of the chemical mechanical grinding. Good etching and chemical mechanical grinding process uniformity is essential for the uniformity of the whole wafer. Is different from the interconnection between metal low dielectric width adjustable, through hole etching process can drastically change between hole and interconnect wire dielectric width, hole etching on the metal mask of high selectivity, SAV (via) self - aligned process than lower than PT (punch through) process has been wider width of dielectric, both in the hole after etching, or in a station type etching or chemical mechanical polishing after all saw significant difference between the two. However, the SAV process has a relatively small size at the bottom of the through-hole, corresponding to a higher through-hole contact resistance. Generally speaking, a compromise between the two processes is needed in engineering.