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Influence of plasma etching on SM

  • Categories:Industry News
  • Author:plasma cleaning machine-surface treatment equipment-CRF plasma machine-Sing Fung Intelligent Manufacturing
  • Origin:
  • Time of issue:2021-01-24
  • Views:

(Summary description)Integrated circuit chips are placed at a certain temperature for a certain period of time, but no current is applied. In some cases, we can also observe the presence of gaps or holes in metal wires, or even complete disconnection. This phenomenon usually occurs under the action of stress transfer (SM). When a metal is subjected to a mechanical stress greater than its yield stress, the metal will undergo a time-dependent plastic deformation. Under fixed mechanical stress, the continuous deformation over time is called creep, and the creep deformation will continue until the stress level falls below the yield stress or until failure occurs. In fact, stress transfer in IC is the metal atom transport process caused by mechanical stress, and its failure is usually driven by creep. In essence, it is the stress release in the chip metal interconnection layer, and one of the results of stress release is the formation of cavity in the metal layer. The mechanical stress is caused by many high-temperature processes in the metal interconnection of integrated circuits and the insulating layer protection process. Due to the different thermal expansion coefficients of metal materials and insulating materials, these high-temperature processes will introduce a large stress in the metal layer aluminum or copper, and the size of the mechanical stress is inversely proportional to the temperature. The nucleation or growth of the cavity in the metal layer caused by stress is a spreading process, which is proportional to temperature. Under the combined effect of mechanical stress and diffusion, the rate of cavity nucleation induced by stress transfer reaches the peak at a certain temperature. This temperature, depending on the properties of the conductor and the surrounding insulator, is generally about 150~200℃. Under the action of stress gradient, the void on the copper grain boundary moves and aggregates to form the void. The bottom of the copper interconnection through hole is a discontinuous structure composed of a variety of metal materials, and its stress is relatively small, so the vacancy tends to move and gather toward the bottom of the through hole. The surrounding copper grain boundary and the interface between copper and dielectric barrier layer provide the source of the vacancy. When a single through hole is placed on a wide copper wire, the effect is severe, because the wide copper wire can provide enough space for the cavity to grow and form a circuit break. The phenomenon of stress transfer can be described by the creep rate model proposed by McPherson and Dunn, whose failure time model is TF = B0 (T0) - nexp (Ea/kBT) (7 to 17) Where, T0 is the temperature of the metal without stress, and is approximately the temperature of deposition for Cu. N is the temperature difference exponential factor; Ea is the activation energy associated with metal diffusion. In engineering, the sample is usually baked at a specific temperature for a specific time, and the ratio of resistance change before and after baking is used to evaluate SM. TEM images of the samples with the contact resistance of the through hole increased by 85% and 200% after baking respectively show that when the cavity is just under the through hole, the resistance increases more greatly. According to the principle of Sm, the film deposition process has a great influence on Sm, such as the microstructure control of Cu deposition, the sputtering amount of the underlying metal during the deposition of metal barrier layer, the control of dielectric thermal expansion coefficient, the influence of alloys in copper, etc. The influence of etching on SM is mainly in two aspects. One is the morphology of the through-hole after etching. If a small palisade morphology appears at the junction of the groove and through-hole, the cavity will appear in the through-hole after copper filling, resulting in the early failure of SM. Second is a hole in the bottom of the polymer residues left much as well as to the bottom of the copper surface Treatment, such as Zhou discusses the different etching processing (Post Etch Treatment, PET) technology on the impact of SM, using N2 PET than CO2 / H2 gas can better remove polymer residues at the bottom of the hole, and to restore of copper at the bottom of the hole, significantly improve the performance of SM.

Influence of plasma etching on SM

(Summary description)Integrated circuit chips are placed at a certain temperature for a certain period of time, but no current is applied. In some cases, we can also observe the presence of gaps or holes in metal wires, or even complete disconnection. This phenomenon usually occurs under the action of stress transfer (SM). When a metal is subjected to a mechanical stress greater than its yield stress, the metal will undergo a time-dependent plastic deformation. Under fixed mechanical stress, the continuous deformation over time is called creep, and the creep deformation will continue until the stress level falls below the yield stress or until failure occurs. In fact, stress transfer in IC is the metal atom transport process caused by mechanical stress, and its failure is usually driven by creep. In essence, it is the stress release in the chip metal interconnection layer, and one of the results of stress release is the formation of cavity in the metal layer.



The mechanical stress is caused by many high-temperature processes in the metal interconnection of integrated circuits and the insulating layer protection process. Due to the different thermal expansion coefficients of metal materials and insulating materials, these high-temperature processes will introduce a large stress in the metal layer aluminum or copper, and the size of the mechanical stress is inversely proportional to the temperature. The nucleation or growth of the cavity in the metal layer caused by stress is a spreading process, which is proportional to temperature. Under the combined effect of mechanical stress and diffusion, the rate of cavity nucleation induced by stress transfer reaches the peak at a certain temperature. This temperature, depending on the properties of the conductor and the surrounding insulator, is generally about 150~200℃. Under the action of stress gradient, the void on the copper grain boundary moves and aggregates to form the void. The bottom of the copper interconnection through hole is a discontinuous structure composed of a variety of metal materials, and its stress is relatively small, so the vacancy tends to move and gather toward the bottom of the through hole. The surrounding copper grain boundary and the interface between copper and dielectric barrier layer provide the source of the vacancy. When a single through hole is placed on a wide copper wire, the effect is severe, because the wide copper wire can provide enough space for the cavity to grow and form a circuit break.
The phenomenon of stress transfer can be described by the creep rate model proposed by McPherson and Dunn, whose failure time model is
TF = B0 (T0) - nexp (Ea/kBT) (7 to 17)
Where, T0 is the temperature of the metal without stress, and is approximately the temperature of deposition for Cu. N is the temperature difference exponential factor; Ea is the activation energy associated with metal diffusion.
In engineering, the sample is usually baked at a specific temperature for a specific time, and the ratio of resistance change before and after baking is used to evaluate SM. TEM images of the samples with the contact resistance of the through hole increased by 85% and 200% after baking respectively show that when the cavity is just under the through hole, the resistance increases more greatly.
According to the principle of Sm, the film deposition process has a great influence on Sm, such as the microstructure control of Cu deposition, the sputtering amount of the underlying metal during the deposition of metal barrier layer, the control of dielectric thermal expansion coefficient, the influence of alloys in copper, etc. The influence of etching on SM is mainly in two aspects. One is the morphology of the through-hole after etching. If a small palisade morphology appears at the junction of the groove and through-hole, the cavity will appear in the through-hole after copper filling, resulting in the early failure of SM. Second is a hole in the bottom of the polymer residues left much as well as to the bottom of the copper surface Treatment, such as Zhou discusses the different etching processing (Post Etch Treatment, PET) technology on the impact of SM, using N2 PET than CO2 / H2 gas can better remove polymer residues at the bottom of the hole, and to restore of copper at the bottom of the hole, significantly improve the performance of SM.

  • Categories:Industry News
  • Author:plasma cleaning machine-surface treatment equipment-CRF plasma machine-Sing Fung Intelligent Manufacturing
  • Origin:
  • Time of issue:2021-01-24 10:00
  • Views:
Information

Influence of plasma etching on SM:

Integrated circuit chips are placed at a certain temperature for a certain period of time, but no current is applied. In some cases, we can also observe the presence of gaps or holes in metal wires, or even complete disconnection. This phenomenon usually occurs under the action of stress transfer (SM). When a metal is subjected to a mechanical stress greater than its yield stress, the metal will undergo a time-dependent plastic deformation. Under fixed mechanical stress, the continuous deformation over time is called creep, and the creep deformation will continue until the stress level falls below the yield stress or until failure occurs. In fact, stress transfer in IC is the metal atom transport process caused by mechanical stress, and its failure is usually driven by creep. In essence, it is the stress release in the chip metal interconnection layer, and one of the results of stress release is the formation of cavity in the metal layer.

Influence of plasma etching on SM

The mechanical stress is caused by many high-temperature processes in the metal interconnection of integrated circuits and the insulating layer protection process. Due to the different thermal expansion coefficients of metal materials and insulating materials, these high-temperature processes will introduce a large stress in the metal layer aluminum or copper, and the size of the mechanical stress is inversely proportional to the temperature. The nucleation or growth of the cavity in the metal layer caused by stress is a spreading process, which is proportional to temperature. Under the combined effect of mechanical stress and diffusion, the rate of cavity nucleation induced by stress transfer reaches the peak at a certain temperature. This temperature, depending on the properties of the conductor and the surrounding insulator, is generally about 150~200℃. Under the action of stress gradient, the void on the copper grain boundary moves and aggregates to form the void. The bottom of the copper interconnection through hole is a discontinuous structure composed of a variety of metal materials, and its stress is relatively small, so the vacancy tends to move and gather toward the bottom of the through hole. The surrounding copper grain boundary and the interface between copper and dielectric barrier layer provide the source of the vacancy. When a single through hole is placed on a wide copper wire, the effect is severe, because the wide copper wire can provide enough space for the cavity to grow and form a circuit break.
The phenomenon of stress transfer can be described by the creep rate model proposed by McPherson and Dunn, whose failure time model is
TF = B0 (T0) - nexp (Ea/kBT) (7-17)
Where, T0 is the temperature of the metal without stress, and is approximately the temperature of deposition for Cu. N is the temperature difference exponential factor; Ea is the activation energy associated with metal diffusion.
In engineering, the sample is usually baked at a specific temperature for a specific time, and the ratio of resistance change before and after baking is used to evaluate SM. TEM images of the samples with the contact resistance of the through hole increased by 85% and 200% after baking respectively show that when the cavity is just under the through hole, the resistance increases more greatly.
According to the principle of Sm, the film deposition process has a great influence on Sm, such as the microstructure control of Cu deposition, the sputtering amount of the underlying metal during the deposition of metal barrier layer, the control of dielectric thermal expansion coefficient, the influence of alloys in copper, etc. The influence of etching on SM is mainly in two aspects. One is the morphology of the through-hole after etching. If a small palisade morphology appears at the junction of the groove and through-hole, the cavity will appear in the through-hole after copper filling, resulting in the early failure of SM. Second is a hole in the bottom of the polymer residues left much as well as to the bottom of the copper surface Treatment, such as Zhou discusses the different etching processing (Post Etch Treatment, PET) technology on the impact of SM, using N2 PET than CO2 / H2 gas can better remove polymer residues at the bottom of the hole, and to restore of copper at the bottom of the hole, significantly improve the performance of SM.

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