Plasma surface processor Polysilicon gate etching

Plasma surface processor Polysilicon gate etching:

When the CMOS process extends to 65nm or below, the etching manufacturing of plasma surface processor gate faces many challenges. As a key technology to control channel length, the pattern of polysilicon gate is closely related to the performance of the device, which affects the whole body. Moore's law promotes yellow light graphics technology from 248nm wavelength light source technology to 193nm wavelength light source technology. This transition was achieved in 2012 with a graphics resolution of 30nm. However, the chemical composition of 193nm photoresist is very different from that of 248nm photoresist, and its anti-etching ability is poor under harsh plasma environment. In order to ensure the exposure process window, the 193nm photoresist is needed to be thinner. In this case, grid graphic dimension control, such as feature size, line width uniformity, wall Angle, side wall shape (concave, protruding) and line width roughness, etc. are all process parameters requiring strict control.

The problem of grid wall roughness can be easily caused by the inorganic hard mask (generally silicon nitride) etching method used by traditional polysilicon gate plasma surface processor. On the other hand, in order to solve the depletion layer problem of polysilicon gate, the polysilicon film layer needs to be doped in advance, which is generally phosphorus doping. Due to the concentration of the doping on the upper part of the polysilicon by ion implantation through the plasma surface processor, severe necking phenomenon occurs when the polysilicon gate is used to remove the hard mask with hot phosphoric acid. Because of the above problems, polysilicon gate etching turned to soft mask etching after 65nm. The etching of traditional polysilicon gate is dominated by halogen gas elements, such as Cl2 and HBr. Predoped polysilicon also has shrinkage phenomenon in halogen gas etching. Han Guo-Lee et al. explained this phenomenon in literature by doping and the coulomb forces of atoms or molecules of halogen gases. The coulomb force of mutual attraction between N-type doped phosphorus or arsenic and chemisorbed halogen gas will increase the etching rate of polysilicon doped plasma surface processor, thus causing shrinkage phenomenon. Zhang et al. studied the effect of HBr/Cl2, HBr/O2 and CF4 on the etching rate of N-type doped polysilicon. The difference of etching rate of CF4 gas in N-doped polysilicon and undoped polysilicon is small, within 5%. The etching rate difference of HBr/O2 is more than 20%, while the etching rate difference of HBr/Cl2 is between the two, about 13%. Therefore, it is a better choice to use CF4 when etching n-type doped polysilicon located in the upper half of polysilicon gate. Because poly gate lithography to stop on the gate oxide silicon, so when using the CF4, gas was fed main etching step after etching the upper half of doped polysilicon, etching the remaining 20% of the lower part of the polysilicon gate etching steps we need to adopt gets/O2 gas etching, in order to realize the plasma surface treatment machine polycrystalline silicon etching high selectivity of gate oxide silicon. As mentioned above, the etching rate of HBr/O2 on N-type doped polysilicon is 20% higher than that of non-hetero polysilicon, which is prone to generate neck shrinking effect. Therefore, the over-etching amount of HBr/O2 should be strictly controlled, generally 30% is better. Too little over-etching amount will lead to long feet on the side wall bottom of the polysilicon gate, and too much over-etching amount will lead to the enhancement of upper neck shrinking effect.

Although HBr/O2 etching process with a higher etching selection ratio for gate silicon oxide is used in plasma surface treatment, it is still easy to cause silicon perforation and silicon damage. The occurrence of silicon perforations is generally due to excessive etching in the main etching step, the touch of gate silicon oxide, or the decrease of etching selection ratio due to the insufficient optimization of HBr/O2 process. However, the Silicon damage caused by polysilicon grid etching is usually detected by transmission electron microscope without corrosion Recess. The cause is not directly related to the etch selection ratio. Due to the decrease of saturation current caused by silicon damage, it is necessary to strictly control the bulk silicon damage during any polysilicon gate etching. Principle of bulk silicon damage caused by polysilicon gate etching in plasma surface treatment Due to the consideration of equivalent silicon oxide thickness, the gate oxide layer is as thin as 1~2 nanometers in the process below 65nm. In HBr/O2 plasma, HBr decomposes hydrogen ions, because the mass of hydrogen ions is very small, under the acceleration of the electric field, high-energy hydrogen ions can pass through gate silicon oxide and inject into the bulk silicon up to 10nm deep, causing dislocation defects in the bulk silicon, and then oxygen atoms are more likely to enter the bulk silicon destroyed by human and form an oxide layer. The oxide layer is removed during subsequent cleaning, resulting in damage to the body silicon. Under the same electric field acceleration condition, the depth of damage layer generated by HBr/O2 gas plasma is 10nm. Without the participation of HBr gas, the depth of the si damage layer is only about 2nm under the condition of O2 gas alone. It can be seen that to solve the damage problem of bulk silicon, the electric field intensity of accelerating hydrogen ions should be reduced first. On the premise that the side wall morphology of polysilicon gate can be maintained, the bias voltage can be reduced from 80V to 60V, and the volume silicon damage can be reduced from 8.5a to 6.3A. Compared with the conventional continuous plasma, pulsed plasma of PLASMA surface processor can effectively reduce the electric field intensity. In the synchronous pulsed plasma, the thickness of the volume silicon damage layer is only 20% of that of the continuous plasma process, which represents the direction of plasma etching in the future.

The characteristic size of the polysilicon gate directly determines the channel length of the device, so the size uniformity inside the chip and the characteristic size change control between the chip are the most important priorities in the polysilicon gate etching. The characteristic size of the polysilicon gate is determined by the etching of amorphous carbon sandwich structure. Therefore, in the etching of sandwich structure of plasma surface processor, feature size modification step is added. The dressing step is dominated by the isotropic etching of high fluorocarbon ratio gases with fewer byproducts, such as the etching of CF4 or NF3. The relationship between the etching time of dressing step and the change of characteristic size is called dressing curve. Through the dressing curve, the linear interval of the dressing T step is found out, and then the adjustable range of the dressing process is obtained. By adjusting the time of the dressing step, the characteristic size of the polysilicon gate can be precisely fine-tuned. At the same time, through the advanced process control, according to the change of the exposure size, the software system is used to dynamically adjust the dressing step time, and get the stable and consistent characteristic size of polysilicon gate. The characteristic size of the optical resistance after yellow light processing is measured, and the difference with the target value is fed back to the finishing time of the subsequent polysilicon gate etching, which is called forward feedback. This feedback can effectively eliminate the optical resistance characteristic size error caused by yellow light process. However, the difference between the measured value of the characteristic size and the target value after etching by the plasma surface processor can be fed back to the modification of the dressing curve, so as to eliminate the influence of the etching cavity condition on the characteristic size, which is called post-feedback.

The characteristic size uniformity of polysilicon gate determines the convergence degree of saturation current. At present, the mainstream polysilicon gate etching machines are equipped with multi-area temperature-controlled electrostatic chuck. By controlling the temperature of different areas on the chip, the adsorption of by-products on the side wall of the line can be controlled to control the characteristic size of the line. There are two types of traditional electrostatic chuck and four types of electrostatic chuck, which can only improve the difference of the characteristic size of different ring areas. Today's plasma surface processing equipment has been developed with a more powerful grid thermostatic chuck that can independently control a smaller area on the chip, more effectively improving asymmetric feature size differences.

In addition to the adjustment of the etching process of plasma surface processor, it is also a mature and effective method to obtain a new exposure condition with pre-compensated energy and improve the uniformity of the characteristic size in the chip by collecting a large amount of data of the characteristic size after etching and using special software analysis. The practice shows that the characteristic size uniformity can be improved by 30% by this method.